The present invention is directed to a method of forming interconnects with air gaps and, more particularly, to a method wherein a sacrificial dielectric layer is deposited to control the depth and profile of the air gap.
Device interconnections in modern day semiconductor chips typically have multilevel structures containing patterns of metal wiring layers that are encapsulated in an insulator. The insulator material is called the interlevel dielectric. Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the metal wiring.
Through their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed and thereby chip performance. Signal-propagation delays are due to RC time constants wherein “R” is the resistance of the on-chip wiring, and “C” is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material and by using interlevel dielectrics (ILDs) with lower dielectric constants, k.
A preferred metal/dielectric combination for low RC interconnect structures is copper metal with a dielectric such as SiO2 (k˜4.0). Due to difficulties in subtractively patterning copper, copper-containing interconnect structures are typically fabricated by a damascene process. In a typical damascene process, metal patterns that are inset in a layer of dielectric are formed by the steps of: (i) etching holes (for vias) or trenches (for wiring) into the interlevel dielectric; (ii) optionally, lining the holes or trenches with one or more adhesion or diffusion barrier layers; (iii) overfilling the holes or trenches with a metal wiring material; and (iv) removing the metal overfill by a planarizing process such as chemical-mechanical polishing (CMP), leaving the metal even with the upper surface of the dielectric.
The above-mentioned processing steps can be repeated until the desired number of wiring and via levels have been fabricated.
Replacing the silicon dioxide with a low κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds and lower heat dissipation. One such example of a low k material is a silicon, carbon, oxygen and hydrogen compound known as SiCOH.